FIFO接口的通用UART串口设计VHDL代码VIVADO仿真

名称：FIFO接口的通用UART串口设计VHDL代码VIVADO仿真

软件：VIVADO

语言：VHDL

代码功能：

FIFO接口的通用UART串口设计

1、发送使用FIFO接口，只需将数据写入FIFO，即可完成UART协议输出

2、默认波特率115200 ,1位起始位，8位数据位，1位停止位，1位校验位

3、参数可调如下：

uart_baudrate<="11100001000000000";--115200

uart_data_len? ?<= "1000";--8bit--输入数据位长度

uart_stop_len? ?<= "01"? ;--输入停止位长度

uart_check_len? <= '1'? ?;--输入校验位长度

uart_check_mode <= '0'? ?;--输入校验位奇偶

FPGA代码Verilog/VHDL代码资源下载：www.hdlcode.com

演示视频：

设计文档：

1. 工程文件

2. 程序文件

3. 程序编译

4. RTL图

5. Testbench

控制往FIFO连续写入00000001~00001010共10个数

6. 仿真图

整体仿真图

往FIFO连续写入00000001~00001010共10个数

串口依次输出01~0a

FIFO控制模块

Tx发送模块

Rx接收模块

波特率控制模块

部分代码展示:

LIBRARY?ieee;
???USE?ieee.std_logic_1164.all;
???USE?ieee.std_logic_unsigned.all;
???USE?ieee.std_logic_arith.all;
--接收模块
ENTITY?uart_rx?IS
???PORT?(
??????clk??????????????????:?IN?STD_LOGIC;
??????rst_n????????????????:?IN?STD_LOGIC;
??????
??????data_len?????????????:?IN?STD_LOGIC_VECTOR(3?DOWNTO?0);--数据长度--?5~8
??????stop_len?????????????:?IN?STD_LOGIC_VECTOR(1?DOWNTO?0);--停止位长度--?1~2
??????check_len????????????:?IN?STD_LOGIC;--校验位长度--?0~1
??????check_mode???????????:?IN?STD_LOGIC;--奇偶--?0~1
??????
??????baud16_tick??????????:?IN?STD_LOGIC;
??????
??????uart_rx_buf_wr_en????:?OUT?STD_LOGIC;--接收使能
??????uart_rx_buf_wr_data??:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0);--接收数据
??????
??????uart_rx_err??????????:?OUT?STD_LOGIC;
??????
??????uart_rxd?????????????:?IN?STD_LOGIC
???);
END?uart_rx;
ARCHITECTURE?trans?OF?uart_rx?IS
???
--???SIGNAL?uart_rxd_sync_r???????????:?STD_LOGIC_VECTOR(2?DOWNTO?0);
???
???SIGNAL?uart_rxd_bit_inv??????????:?STD_LOGIC;
???
???SIGNAL?Bau16_Tick_shift_r????????:?STD_LOGIC_VECTOR(1?DOWNTO?0);
???SIGNAL?Bau16_Tick_rising?????????:?STD_LOGIC;
???
???SIGNAL?state?????????????????????:?STD_LOGIC_VECTOR(3?DOWNTO?0);
???SIGNAL?next_state????????????????:?STD_LOGIC_VECTOR(3?DOWNTO?0);
???SIGNAL?cnt_baud16_tick???????????:?STD_LOGIC_VECTOR(3?DOWNTO?0);
???SIGNAL?cnt_rx_bit????????????????:?STD_LOGIC_VECTOR(3?DOWNTO?0);
???
???SIGNAL?rx_shift_reg??????????????:?STD_LOGIC_VECTOR(8?DOWNTO?0);
???
???SIGNAL?rx_check_sum??????????????:?STD_LOGIC;
???SIGNAL?local_check_sum???????????:?STD_LOGIC;
???SIGNAL?uart_rx_buf_wr_data_buf?:?STD_LOGIC_VECTOR(7?DOWNTO?0);
BEGIN
???--?Drive?referenced?outputs
???uart_rx_buf_wr_data?<=?uart_rx_buf_wr_data_buf;--输出接收数据
--???PROCESS?(clk)
--???BEGIN
--??????IF?(clk'EVENT?AND?clk?=?'1')?THEN
--?????????uart_rxd_sync_r?<=?(uart_rxd_sync_r(1?DOWNTO?0)?&?uart_rxd);--移位
--??????END?IF;
--???END?PROCESS;
???
???PROCESS?(clk)
???BEGIN
??????IF?(clk'EVENT?AND?clk?=?'1')?THEN
?????????uart_rxd_bit_inv?<=?uart_rxd;--同步到时钟下
??????END?IF;
???END?PROCESS;
???
???PROCESS?(clk)
???BEGIN
??????IF?(clk'EVENT?AND?clk?=?'1')?THEN
?????????Bau16_Tick_shift_r?<=?(Bau16_Tick_shift_r(0)?&?baud16_tick);
??????END?IF;
???END?PROCESS;
???PROCESS?(clk)
???BEGIN
??????IF?(clk'EVENT?AND?clk?=?'1')?THEN
?????????if(Bau16_Tick_shift_r?=?"01")then--检测Bau16_Tick_shift_r上升沿
Bau16_Tick_rising<='1';--上升沿
else
Bau16_Tick_rising<='0';
end?if;
??????END?IF;
???END?PROCESS;
???
--状态机
???PROCESS?(clk,?rst_n)
???BEGIN
??????IF?((NOT(rst_n))?=?'1')?THEN
?????????state?<=?"0000";
??????ELSIF?(clk'EVENT?AND?clk?=?'1')?THEN
?????????state?<=?next_state;
??????END?IF;
???END?PROCESS;

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